ram question

  • psuedofy
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Post 3+ Months Ago

ive read somewhere about the battle between ram stick speeds and tight timings....which is what i want to be looking for?
i heard that having tight timings and a lower clock speed could sometimes beat a stick with higher clock.

my question is what do the numbers (timings): 2-2-2-4, 4-4-4-12 (im just guessing these numbers), but what do those numbers mean?
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Post 3+ Months Ago

  • Dangles
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Post 3+ Months Ago

http://www.nforcershq.com/forum/viewtopic.php?t=23936 wrote:
Decoding Memory Timings: Example Corsair XMS2700 @ 2-3-3-6-1T
------------------------------------------------------------------------------
CAS Latency: 2
RAS Precharge (tRP): 3
RAS-to-CAS Delay (tRCD): 3
Bank cycle time (or tRAS): 6
Command Rate: 1T

CAS:
CAS latency is basically the number of clock cycles (or Ticks, denoted with T) between the receipt of a "read" command and when the ram chip actually starts reading. Obviously, lower numbers will result in less of a delay when memory is being read from. Corsair's website claims a low single digit % gain from CAS-3 to CAS-2. Memory can be basically visualized as a table of cell locations, and the CAS delay is invoked every time the column changes (which is far more often than the row changing). The differences in memory bandwidth concerning CAS latency were non-existent (and it is just as likely that any recorded performance gains are attributed to random events, as performance gains were not at all consistent). There was no significant gain in memory bandwidth from adjusting CAS latencies.

Precharge to Active (tRP):
The Precharge to Active timing controls the length of the delay between the precharge and activation commands. This influences row activation time which is taken into account when memory has hit the last column in a specific row, or when an entirely different memory location is requested. The gain from optimizing the tRP value (3T to 2T) seemed to scale with higher FSBs (10MB/sec at 100 FSB, 20MB/sec at 166 FSB), giving a consistent .1% increase in performance. I highly doubt that this .1% in memory bandwidth would translate to a noticeable (or significant) real world increase.

Active to CMD (Trcd):
This timing controls the length of the delay between when a memory bank is activated to when a read/write command is sent to that bank. This basically comes into play when the memory locations are not accessed in a linear fashion (because in a linear fashion, the current bank is already activated). This option gave a consistent 20-30 MB/sec gain in memory bandwidth (3T to 2T), with the results pointing to a slight scaling at lower CAS latencies and higher FSBs.

Active to Precharge (tRAS):
The Active to Precharge timing controls the length of the delay between the activation and precharge commands -- basically how long after activation can the access cycle be started again. This influences row activation time which is taken into account when memory has hit the last column in a specific row, or when an entirely different memory location is requested. As with CAS, the performance gain (7T to 6T) was inconsistent, and possibly could be attributed to random variables.

DRAM Command Rate (self-abbreviated DRC):
I'm going to take a quote from Adrian's Rojak Pot in order to explain this setting: "This BIOS feature controls how long the memory controller latches on and asserts the command bus. The lower the value, the faster the the memory controller can send commands out." A faster DRAM Command Rate (3T to 2T) results in a consistent 30MB/sec gain in memory bandwidth.


Found this at the link in the quote line.

Dangles

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